About me

Cornell University  ·  Sep. 2021 – Present
Ph.D. candidate in Electrical and Computer Engineering

Cornell University  ·  Sep. 2021 – Dec. 2025
M.S. in Electrical and Computer Engineering

Tsinghua University  ·  Sep. 2016 – Jun. 2020
B.E. in Electronic Engineering

AMD Research and Advanced Development  ·  Jan 2026 – Present
Ph.D. Research Associate, AMD RAD
Mentors: Erwei Wang, Samuel Bayliss
An Agentic System for Efficient LLM Deployment on AIE NPUs

• Built an agentic system that guides coding agents through kernel development and model composition for end-to-end LLM deployment on AMD XDNA™ 2 NPUs, combining a kernel database, reusable NPU engineering skills, and staged feedback on top of the open-source MLIR-AIR compiler flow. An early version was accepted by MLArchSys (co-located with ISCA 2026).
• Autonomously deployed multiple previously unsupported LLMs end-to-end, achieving significant energy-efficiency gains over an iGPU baseline and large prefill and decode speedups over the coding agent alone, with less agent time and lower API cost.
• Extended single-token decode megakernels to support DFlash speculative decoding through the agentic workflow, achieving 1.7–2.2× decode speedups over a production inference solution’s autoregressive decoding.

ByteDance  ·  Aug 2024 – Dec 2024
Research Scientist Intern, Machine Learning System team, Seed Foundation
Mentors: Wenlei Bao, Li-Wen Chang
Characterizing High-Performance LLM Kernels on NVIDIA GPUs

• Benchmarked GEMM and grouped GEMM across cuBLAS, Triton, and CUTLASS over a range of problem sizes, data types, and GPU architectures, using the CUTLASS profiler and Triton autotuning to find each library’s best configuration.
• Identified warp specialization combined with the Tensor Memory Accelerator (TMA) on Hopper GPUs as the key to reaching peak performance, and analyzed why this design lets kernels overlap data movement with Tensor Core computation.

NVIDIA  ·  May 2024 – Aug 2024
Deep Learning Training Performance Intern, End-to-End Training Performance team (working on MLPerf-Training)
Mentors: Rachit Garg, Burc Eryilmaz
LLM Training Toolbox: Memory Footprint Analyzer & Configuration Autotuner

• Built a memory footprint analyzer that collects and analyzes memory snapshots for peak-memory debugging and memory-leak detection in LLM training, and integrated it into NeMo and the MLPerf training pipeline; the tool helped teammates debug memory issues with CUDA Graphs.
• Built an autotuner that searches the large training-configuration space (TP, PP, CP sizes, TP-overlap configs, etc.) for the best setup given a model and hardware, delivering a 1.1% end-to-end speedup over the heavily hand-tuned MLPerf submission config.

Alibaba DAMO Academy  ·  Jul. 2020 – Jan. 2021
Research Intern, Computing Technology Lab
Mentor: Yuanwei Fang
Neural Program Sampling for Fast Microarchitecture Simulation

• Contributed to Neural Program Sampling (NPS), a GNN-based framework that learns execution embeddings from code structure and runtime state to select representative program intervals for simulation, outperforming SimPoint by up to 63%.
• Built the NPS-gem5 evaluation testbed by extending gem5 to emit detailed-simulation statistics at specified instruction intervals, enabling fast and flexible evaluation of sampling accuracy.

Cornell University  ·  Sep. 2021 – Present
Ph.D. candidate, Zhang Research Group, Computer Systems Lab
Advisor: Prof. Zhiru Zhang

Agentic Kernel Generation Across Hardware Targets

• Prototyped an LLM agentic workflow that generates and tunes kernels for CPUs, GPUs, and the AMD AI Engine through a feedback loop of correctness checking, error debugging, and iterative optimization, grounded in curated AI Engine API documentation; this work laid the foundation for the agentic NPU deployment system developed at AMD.

HeuriGym: An Agentic Benchmark for LLM-Crafted Heuristics in Combinatorial Optimization

• Co-developed HeuriGym (ICLR’26, core contributor), an open-source agentic benchmark in which LLMs iteratively write, execute, and refine heuristics for nine combinatorial optimization problems, with a continuously updated public leaderboard.
• Contributed the technology-mapping problem from the electronic design automation (EDA) domain, including its formalization and expert solution; it remains among the hardest problems in the suite, where even the latest frontier models score lowest.

Rapid GPU-Based Pangenome Graph Layout

• Developed the first GPU implementation of path-guided SGD for pangenome graph layout, achieving a 57.3× average speedup on an NVIDIA A100 over a 32-thread CPU baseline and reducing layout time for 24 human whole-chromosome pangenomes from hours to minutes without quality loss. The work was accepted by SC’24 and integrated into the ODGI pangenome analysis toolkit.
• Characterized the workload as memory-bound with highly irregular access patterns, then designed CUDA optimizations including a cache-friendly data layout, coalesced random-number-generator states, and warp merging to reduce branch divergence.
• Proposed sampled path stress, a sampling-based layout-quality metric that reduces evaluation cost from quadratic to linear time complexity, and used it to explore performance-quality trade-offs, gaining a further 1.5× speedup via warp-level data reuse.

Analysis and Optimization of GNN-Based Recommender Systems on Persistent Memory

• Showed that Intel Optane persistent memory enables single-machine training of GNN-based recommender systems on billion-edge graphs, outperforming distributed training by over 30× for deep GNN models at less than half the memory cost.
• Built and tuned the distributed training baseline with DistDGL on a six-server CPU cluster, running NGCF and LightGCN on graphs with up to one billion edges for an end-to-end comparison against single-machine Optane training.

UCLA  ·  Jun. 2019 – Sep. 2019
Research Intern, VAST Lab
Advisor: Prof. Jason Cong
HeteroHalide: An End-to-End Compilation System from Image Processing DSL to Efficient FPGA Acceleration

• Proposed HeteroHalide, an end-to-end compilation flow from Halide to FPGA accelerators, including a Halide-to-HeteroCL code generator in C++ and scheduling extensions that emit lower-level primitives at the spatial-architecture backend. The work was accepted by FPGA’20.
• Showed that the generated accelerators outperform both a 28-core CPU (4.15× speedup, 11.7× energy efficiency) and the state-of-the-art Halide-to-FPGA compiler (2–4× throughput), while requiring only moderate changes to Halide schedules.

Tsinghua University  ·  Nov. 2018 – Jun. 2019
Research Assistant, NICS-EFC Lab (Energy Efficient Computing Group)
Advisor: Prof. Yu Wang
Hardware-Friendly Neural Network Compression

• Studied hardware-friendly model compression for efficient deployment, quantifying how low-bit quantization, pruning, and knowledge distillation trade off model size against accuracy.